This invention relates to a method of fabricating a semiconductor integrated circuit device, to a semiconductor integrated circuit device technique; and, in particular, to a method of fabricating a semiconductor integrated circuit device comprising an embedded interconnection having copper as the main conducting layer, and an effective technique applied to a semiconductor integrated circuit device.
In a technique for forming interconnections comprising semiconductor integrated circuit devices, semiconductor devices, electronic circuit devices and electronic devices, a conducting film, such as, for example, aluminum or tungsten, is deposited over an insulating film and is patterned by ordinary photolithography and dry etching.
However, in this interconnection forming technique, as devices and interconnections comprising semiconductor integrated circuit devices become finer, interconnection resistances are largely increasing, interconnection delays are occurring, and a limit is being reached to further performance improvements of the semiconductor integrated circuit devices.
In recent years, an interconnection forming technique known as the Damascene method has been developed. This Damascene method may be broadly distinguished into two types, i.e., the Single Damascene method and the Dual Damascene method.
In the Single Damascene method, after forming an interconnection slot in an insulating film, for example, a main conducting layer for forming interconnections is deposited over this insulating film and in the interconnection slot, and an embedded interconnection in the interconnection slot is formed by polishing this main conducting layer by, for example, CMP (Chemical Mechanical Polishing), so that it is left only in the interconnection slot.
In the Dual Damascene method, after forming a connecting hole to connect with the interconnection slot and a substrate interconnection in the insulating film, a main conducting layer for forming interconnections is deposited over this insulating film and in the interconnection slot and connecting hole, and an embedded interconnection in the interconnection slot and the connecting hole is formed by polishing this main conducting layer by, for example, CMP (Chemical Mechanical Polishing), so that it is left only in the interconnection slot and connecting hole.
In both methods, a material such as copper or the like is used as the material of the main conducting layer of the interconnections from the viewpoint of improving the performance of the semiconductor integrated circuit device. Copper has the advantage that, compared to aluminum, its resistance is lower and its permitted current for reliability is more than two orders of magnitude higher. Hence, the film can be made thinner to obtain the same interconnection resistance, and the capacitance between adjacent interconnections can be reduced.
However, compared to other metals, such as aluminum or tungsten, it diffuses easily in the insulating film if copper is used as the interconnection material, therefore, it is necessary to form a thin conducting barrier film to prevent diffusion of copper on the surface of the main conducting layer including copper (bottom surface and side surfaces), i.e., on the inner wall surfaces (side surfaces and bottom surface) of the interconnection slot. There is also a technique to prevent diffusion of copper in the embedded interconnection from the upper surface of the embedded interconnection into the insulating film by depositing a cap film including, for example, silicon nitride so as to cover the upper surface of the embedded interconnection over the entire surface on the upper surface of the insulating film in which the interconnection slot is formed.
This kind of embedded interconnection technique is mentioned in, for example, Japanese Unexamined Patent Publication No. Hei 10(1998)-154709, wherein the embedded properties of a fine contact hole with a high aspect ratio are improved by forming the embedded interconnection of high purity copper having an oxygen concentration or sulfur concentration not exceeding 3 ppm, thus enhancing the surface diffusion properties and fluidity of the copper.
In Japanese Unexamined Patent Publication No. Hei 11 (1999)-87349, for example, a technique is disclosed wherein, after forming the interconnection slot and connecting hole in the insulating film, a copper film is formed by sputtering using a target having a purity of 99.999 wt % (5N) or higher. In this Publication, to facilitate embedding of the copper, a titanium nitride/titanium film is formed as a barrier layer over the surface of the interconnection slot and connecting hole.
In Japanese Unexamined Patent Publication No. Hei 11(1999)-87509 or Japanese Unexamined Patent Publication No. Hei 11 (1999)-220023, for example, a technique is disclosed wherein the barrier layer on the bottom surface of a via is removed to lower the resistance of the via.
In Japanese Unexamined Patent Publication No. Hei 11 (1999)-16912, for example, a technique is disclosed wherein the oxide layer formed in the interconnection part exposed at the bottom of the connecting hole is eliminated by applying heat, plasma or ultraviolet irradiation in a reducing atmosphere.